lcapossio/fpgaZeroMCP
An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed by GitHub.
Platform-specific configuration:
{
"mcpServers": {
"fpgaZeroMCP": {
"command": "npx",
"args": [
"-y",
"fpgaZeroMCP"
]
}
}
}Add the config above to .claude/settings.json under the mcpServers key.
An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed by GitHub.
Ask your AI to search for cores, pull them in, lint HDL, synthesize a design, or run a simulation — all without leaving your chat window.
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Your AI assistant <--> fpgaZeroMCP (stdio MCP server) <--> OSS tools
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cores/ registry on GitHub
(uart_tx, fifo + any imported)The MCP server runs as a local subprocess. Your AI calls tools on it over JSON-RPC (stdio). The server shells out to Yosys, nextpnr, iverilog, Verilator, and others from OSS CAD Suite — and can pull open-source FPGA cores directly from GitHub.
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| Requirement | Notes | |---|---| | Python 3.11+ | | | OSS CAD Suite | Bundles iverilog, Yosys, nextpnr, Verilator, Verible, GHDL in one download | | LiteX + litex-boards | Optional — only needed for LiteX tools |
Add OSS CAD Suite to your `PA
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